CoBo Meeting Minutes: September 25, 2008
Attendance: Saillant, Pedroza, Wittwer, Pollacco, Usher, Mittig, Bickley
slides:http://www.nscl.msu.edu/~bickley/CoBo/mtg_080925/CoBoMeeting_080925.pdf	

Block Diagram:
	- confirmation that Virtex5 is a good choice for this purpose
	- timestamp and trigger should go to the Mutant not to the InBo
	- question of whether 1FPGA will be sufficient memory for the funcitons to be performed
	- Virtex5 network tests performed at Daresbury showed an ethernet transmission rate of 20MB/s
	- Virtex4 tests showed a rate of 12 MB/s
	- the Ganil and Bordeaux detectors will require optical fiber output for data because these rates are too low
	- the slow controls signal will still be sent over ethernet
	- general feeling that a meeting to discuss the board interfaces with the other components of the system 
	  will be necessary
	
Connectors:
	- temperature => ADC on AsAd will digitize and send the signal to Cobo; will also need to monitor the 
	  temperature of the CoBo
	- need a trigger for the pulser that is contained on each AsAd
	- some discussion of whether a pulser is required for each ASIC, response negative
	- this will require a new connections
	- input from Saclay on required inputs is needed

Starter Kit:
	- will allow speed of connection to ADC and gigabit ethernet to be tested
	- will also test memory needs of desired functionality and whether 2 FPGA's are beneficial
	- question about how the Gb ethernet will be tested if the starter kit does not contain a power pc core
	- response is that ethernet firmware is included in the package to allow these tests

Desired FPGA Functionality:
	- long discussion ensued regarding how complicated/powerful we want to make the CoBo
	- option exists to perform many operations alternatively in the CoBo or later in software
	- opinions mixed about how many operations should be incorporated into the CoBo itself
	- decided to prioritize potential FPGA operations

	(per channel operations: 17F)
	- zero suppression essential
	- time stamp essential - incorporate as a header to each data block being transmitted not each channel
	- baseline subtraction requirement interesting but not essential - (note mixed definitions of what this 
	  means seemed to exist)
	- data compression - worth pursuing via pulse height, width and center of gravity extraction
	- CFD - not needed
	- pileup nonessential - requires recognition of 2 overlapping signals; unclear how to do this when only have 
	  channel based information
	- unwanted signal rejection nonessential - negative pulses, saturated channels

	(overall FPGA operations: 17A-E)
	- general consensus that most of these operations should be handled on the software level not internal to the CoBo
	- presuming the CoBo is designed with sufficient FPGA memory we have the option of rolling out upgraded
	  code versions that include additional functionality at a later date
	- strong feeling that we need to focus now on getting a minimal version operational that meets the rate and 
	  deadtime requirements of the project
	- need to determine how much memory should be allocated for the essential functions and how much memory remains
	- all slow controls will go through the power PC part of the FPGA

General Discussion:
	- strong feeling that additional input is required from the other working groups, particularly the AsAd, 
	  InBo and Mutant
	- after all of the working groups have met a larger organizational meeting will be held to make sure all of 
	  the interfaces have been accounted for (possibly mid-October??)